.. |
AInst.cs
|
|
|
AInstEmitAlu.cs
|
Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104)
|
2018-04-25 23:20:22 -03:00 |
AInstEmitAluHelper.cs
|
Fix corner cases of ADCS and SBFM
|
2018-02-26 15:56:34 -03:00 |
AInstEmitBfm.cs
|
Fix corner cases of ADCS and SBFM
|
2018-02-26 15:56:34 -03:00 |
AInstEmitCcmp.cs
|
|
|
AInstEmitCsel.cs
|
Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store
|
2018-02-25 22:14:58 -03:00 |
AInstEmitException.cs
|
Print guest stack trace on a few points that can throw exceptions
|
2018-04-22 02:48:17 -03:00 |
AInstEmitFlow.cs
|
Stub a few services, add support for generating call stacks on the CPU
|
2018-04-22 01:22:46 -03:00 |
AInstEmitHash.cs
|
Remove unused function from CPU
|
2018-03-14 00:57:07 -03:00 |
AInstEmitMemory.cs
|
|
|
AInstEmitMemoryEx.cs
|
|
|
AInstEmitMemoryHelper.cs
|
Improved logging (#103)
|
2018-04-24 15:57:39 -03:00 |
AInstEmitMove.cs
|
|
|
AInstEmitMul.cs
|
|
|
AInstEmitSimdArithmetic.cs
|
Add Sqxtn_S, Sqxtn_V, Uqxtn_S, Uqxtn_V instructions and Tests (6). (#110)
|
2018-04-29 20:39:58 -03:00 |
AInstEmitSimdCmp.cs
|
Fix FRSQRTS and FCM* (scalar) instructions
|
2018-04-06 10:20:17 -03:00 |
AInstEmitSimdCvt.cs
|
Add MUL (vector by element), fix FCVTN, make svcs use MakeError too
|
2018-03-05 16:18:37 -03:00 |
AInstEmitSimdHelper.cs
|
Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. (#74)
|
2018-04-08 16:08:57 -03:00 |
AInstEmitSimdLogical.cs
|
Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104)
|
2018-04-25 23:20:22 -03:00 |
AInstEmitSimdMemory.cs
|
|
|
AInstEmitSimdMove.cs
|
Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77)
|
2018-04-12 11:52:00 -03:00 |
AInstEmitSimdShift.cs
|
CPU fix for the cases using a Mask with shift = 0
|
2018-03-14 01:59:22 -03:00 |
AInstEmitSystem.cs
|
Add pl:u stub, use higher precision on CNTPCT_EL0 register tick count
|
2018-03-13 21:24:32 -03:00 |
AInstEmitter.cs
|
|
|
ASoftFallback.cs
|
Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104)
|
2018-04-25 23:20:22 -03:00 |
ASoftFloat.cs
|
Implement Frsqrte_S (#72)
|
2018-04-05 20:36:19 -03:00 |